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DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
PC1853
MATRIX SURROUND IC WITH I2C BUS
The PC1853 is a phase shift matrix surround IC. Only 2 speakers on the front side implement wide sound expansion, and by adding rear speakers, rich three-dimensional sound can obtained. The PC1853 can perform all controls (mode switching, volume control and so on) through the I2C bus.
FEATURES
* Any control is possible through the I2C bus. * Surround effect can be realized by only 2 speakers on the front side. * On-chip tone (bass and treble) control circuit. * Level-adjustable output pin for heavy bass sound. * Level-adjustable output pin for AV amplifier. * PC1853-01 : * PC1853-02 : On-chip low boost circuit. On-chip volume and balance control circuits. On-chip L-channel volume and R-channel volume control circuits.
APPLICATION
* TV, audio
ORDERING INFORMATION
Part Number Package 30-pin plastic shrink DIP (400 mil)
PC1853CT-01 PC1853CT-02
"
The information in this document is subject to change without notice. Document No. S10552EJ2V0DS00 (2nd edition) (Previous No. ID-3126) Date Published October 1995 P Printed in Japan
(c)
1995
PC1853
SYSTEM BLOCK DIAGRAM
* TV
Tuner
PIF & SIF
Color, intensity and deflecting Signal processor
RGB output Vertical output
CRT
PC1852
PC1853
L US MTS processor R
PD17002 PD17052 PD17053
PC1310 PC1316C
Surround processor
Power amplifier
Digital tuning controller
SDA SCL
PC2800A Remote control reception PC2801A amplifier
PIN photo diode
2
(1) PC1853-01
BLOCK DIAGRAM
820 k 680 pF 0.082 F MFO 29 2200 pF 0.022 F 12 V 1000 pF - 0.022 F 0.1 F FC1FC2 FC3 FC4 VCC MFI LF1 30 28 2345 15 LF2 6 OFC + 25 22 F 0.1 F LBC 10 9 Volume, balance control/Mute Volume control /Mute DA 18 - + PS1PS2PS3 PS4 - + Phase shifter DA Effect control LPF Offset absorption 1 2 VCC Bass DA Volume Balance DA Rin + Treble 27 DA Volume control /Mute Tone control/ Low boost 1 2 VCC Volume, balance control/Mute Volume control /Mute L + R volume control/Mute DA DA 16 R2 OUT 13 DA 19 BAL-C + - 3.3 F 14 L1 OUT 6800 pF LTC
Tone control/ Low boost Lin +
-
17 L2 OUT
26
22 F
VOL-C + - 3.3 F
LPF
Matrix
-
22 F
R1 OUT
I2C bus interface
11 Rear OUT
PC1853
12 L+R OUT 24 1 2 VCC + 22 F - 22 21 20 23 ADS SDA SCL GND 1 GND RBC 0.1 F 8 7 RTC 6800 pF
3
4
0.082 F MFO - Lin + 26 22 F - Rin + 27 22 F
(2) PC1853-02
820 k 680 pF 2200 pF 0.022 F 12 V 1000 pF - 0.022 F 0.1 F FC1 FC2FC3 FC4 VCC MFI LF1 30 28 2345 15 LF2 6 OFC + 25 22 F 0.1 F LBC 10 9 Volume control /Mute Volume control /Mute DA 18 - + PS1PS2PS3 PS4 - + Phase shifter DA DA Treble DA Volume control /Mute Tone control Volume control /Mute Volume control /Mute L + R volume control/Mute DA 12 L+R OUT 24 1 2 VCC + 22 F - 22 21 20 23 ADS SDA SCL GND 1 GND RBC 0.1 F 8 7 RTC 6800 pF DA 16 R2 OUT 13 19 Effect control LPF Offset absorption 1 2 VCC Bass DA DA RVC + - 3.3 F 14 L1 OUT 6800 pF LTC
29
Tone control
17 L2 OUT
LVC + - 3.3 F
LPF
Matrix
R1 OUT
1 2 VCC
I2C bus interface
11 Rear OUT
PC1853
PC1853
PIN CONFIGURATION (Top View)
(1) PC1853-01
Ground (for Analog) Phase shift filter 1 Phase shift filter 2 Phase shift filter 3 Phase shift filter 4 Low-pass filter 2 R-channel treble capacitor R-channel bass capacitor L-channel treble capacitor L-channel bass capacitor Rear output L+R signal output R-channel signal output 1 L-channel signal output 1 Power supply
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GND FC1 FC2 FC3 FC4 LF2
MFI MFO LF1 Rin Lin OFC
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Monaural filter input Monaural filter output Low-pass filter 1 R-channel signal input L-channel signal input Offset absorption capacitor Reference voltage filter Ground (for I2C bus) Slave address select Serial data (for I2C bus) Serial clock (for I2C bus) Balance offset absorption capacitor Volume offset absorption capacitor L-channel signal output 2 R-channel signal output 2
PC1853CT -01
RTC RBC LTC LBC Rear OUT L+R OUT R1 OUT L1 OUT VCC
1 VCC 2 GND ADS SDA SCL BAL-C VOL-C L2 OUT R2 OUT
5
PC1853
(2) PC1853-02
Ground (for Analog) Phase shift filter 1 Phase shift filter 2 Phase shift filter 3 Phase shift filter 4 Low-pass filter 2 R-channel treble capacitor R-channel bass capacitor L-channel treble capacitor L-channel bass capacitor Rear output L+R signal output R-channel signal output 1 L-channel signal output 1 Power supply
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GND FC1 FC2 FC3 FC4 LF2
MFI MFO LF1 Rin Lin OFC
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Monaural filter input Monaural filter output Low-pass filter 1 R-channel signal input L-channel signal input Offset absorption capacitor Reference voltage filter Ground (for I2C bus) Slave address select Serial data (for I2C bus) Serial clock (for I2C bus) R-channel volume offset absorption capacitor L-channel volume offset absorption capacitor L-channel signal output 2 R-channel signal output 2
PC1853CT -02
RTC RBC LTC LBC Rear OUT L+R OUT R1 OUT L1 OUT VCC
1 VCC 2 GND ADS SDA SCL RVC LVC L2 OUT R2 OUT
6
PC1853
CONTENTS
1. EXPLANATION OF PINS ................................................................................................................
8
2. ATTENTIONS .................................................................................................................................... 16 3. I2C BUS INTERFACE ...................................................................................................................... 17
3.1 Data Transfer ............................................................................................................................................. 3.1.1 3.1.2 3.1.3 3.2.1 3.2.2 3.2.3 Start condition .............................................................................................................................. Stop condition ............................................................................................................................... Data transfer .................................................................................................................................. 1 byte data transfer ....................................................................................................................... Serial data transfer ....................................................................................................................... Acknowledge ................................................................................................................................. 17 17 18 18 18 19 20 20
3.2 Data Transfer Format ...............................................................................................................................
4. EXPLANATION OF EACH COMMAND ......................................................................................... 21
4.1 Subaddress List ........................................................................................................................................ 4.2 Initialization ............................................................................................................................................... 4.3 Surround Function ................................................................................................................................... 4.4 Explanation of Each Command ............................................................................................................... 4.4.1 4.4.2 21 23 24 25 25 32
PC1853-01 ................................................................................................................................... PC1853-02 ...................................................................................................................................
5. ELECTRICAL CHARACTERISTICS ............................................................................................... 35 6. CHARACTERISTIC CURVES .......................................................................................................... 63
6.1 Frequency Response Characteristics in Each Mode ............................................................................ 6.2 Characteristics of Phase Shifter and Rear Output ................................................................................ 6.3 Control Characteristics ............................................................................................................................ 6.4 Input/Output Characteristics, Distortion Rate ....................................................................................... 63 66 68 73
7. MEASURING CIRCUIT .................................................................................................................... 74 8. PACKAGE DIMENSIONS ................................................................................................................ 75
7
PC1853
1. EXPLANATION OF PINS
Table 1-1 Explanation of Pins (1/8)
Pin Number 1 Pin Name GND Equivalent Circuit 15 1 Description Ground for analog signal. Pin voltage: approx. 0.0 V
23 2 FC1
VCC 36 k 36 k 18 k VCC
Capacitor connection pin which determines time constant of phase shifter. Pin voltage: approx. 6.0 V
2 0.1 F
3
FC2
VCC 36 k 36 k 18 k VCC
3 2200 pF
4
FC3
VCC 36 k 36 k 18 k VCC
4 0.022 F
8
PC1853
Table 1-1 Explanation of Pins (2/8)
Pin Number 5 Pin Name FC4 Equivalent Circuit Description Capacitor connection pin which determines time constant of phase shifter. Pin voltage: approx. 6.0 V
VCC 36 k 36 k 18 k VCC
5 0.022 F
6
LF2
VCC
17.7 k
Low-pass filter. Pin voltage: approx. 6.0 V
17.7 k VCC
6 1000 pF
7
RTC
VCC
7.5 k 5.8 k VCC 3 k
Capacitor connection pin for treble boost/cut frequency characteristic of R-channel signal. Pin voltage: approx. 6.0 V
7 6800 pF
8
RBC
VCC
Capacitor connection pin for bass boost/cut frequency characteristic of Rchannel signal. Pin voltage: approx. 6.0 V
6.5 k VCC 3 k
8 0.1 F
9
PC1853
Table 1-1 Explanation of Pins (3/8)
Pin Number 9 Pin Name LTC Equivalent Circuit Description Capacitor connection pin for treble boost/cut frequency characteristic of L-channel signal. Pin voltage: approx. 6.0 V
VCC 7.5 k 5.8 k VCC 3 k
9 6800 pF
10
LBC
VCC
Capacitor connection pin for bass boost/cut frequency characteristic of L-channel signal. Pin voltage: approx. 6.0 V
6.5 k VCC 3 k
10 0.1 F
11
Rear OUT
VCC 4 k VCC
VCC 500 4 k
15 k
11
L-R signal output pin. Select the output signal ((L-R) signal or (L-R) signal) (see 4.4.1(4) or 4.4.2(2) Rear output selection). * (L-R): Phase-shifted. * (L-R) : Not phase-shifted. Pin voltage: approx. 6.0 V
4 k 4 k
12
L+R OUT
VCC 4 k VCC
VCC 500 4 k
L+R signal output pin. Pin voltage: approx. 6.0 V
15 k
12
4 k 4 k
10
PC1853
Table 1-1 Explanation of Pins (4/8)
Pin Number 13 Pin Name R1 OUT
VCC 4 k VCC
Equivalent Circuit
VCC 500 4 k
Description R-channel signal output pin (for main output). Pin voltage: approx. 6.0 V
15 k
13
4 k 4 k
14
L1 OUT
VCC 4 k VCC
VCC 500 4 k
L-channel signal output pin (for main output). Pin voltage: approx. 6.0 V
15 k
14
4 k 4 k
15
VCC
15 1
Supply voltage. Pin voltage: approx. 12.0 V
16
R2 OUT
VCC 4 k VCC
VCC 500 4 k
R-channel signal output pin for external audio processor and so on. Pin voltage: approx. 6.0 V
15 k
16
4 k 4 k
11
PC1853
Table 1-1 Explanation of Pins (5/8)
Pin Number 17 Pin Name L2 OUT
VCC 4 k VCC
Equivalent Circuit
VCC 500 4 k
Description L-channel signal output pin for external audio processor and so on. Pin voltage: approx. 6.0 V
15 k
17
4 k 4 k
18
VOL-C (PC1853-01)
VCC 4 k 500
VCC
Capacitor connection pin which absorbs shock noise of D/A converter for volume control. Pin voltage: approx. 6.0 V
LVC (PC1853-02)
3.3 F
+ 18
4 k
Capacitor connection pin which absorbs shock noise of D/A converter for L-channel volume control. Pin voltage: approx. 6.0 V
19
BAL-C (PC1853-01)
VCC 15 k + 19
VCC 4 k
Capacitor connection pin which absorbs shock noise of D/A converter for balance control. Pin voltage: approx. 4.8 V
RVC (PC1853-02)
3.3 F
500 4 k
Capacitor connection pin which absorbs shock noise of D/A converter for R-channel volume control. Pin voltage: approx. 4.8 V
20
SCL 4 k
Serial clock line pin (clock input for I2C bus). Pin voltage: approx. 0.0 V
20
12
PC1853
Table 1-1 Explanation of Pins (6/8)
Pin Number 21 Pin Name SDA Equivalent Circuit Description Serial data line pin (data input for I2C bus). Pin voltage: approx. 0.0 V
VCC 4 k 21 150 1 k
VCC
1 k
25 k
125 k
22
ADS
Slave address selection pin. Pin voltage: approx. 0.0 V 4 k 22
23
DGND
1
Ground for I2C bus signal. Pin voltage: approx. 0.0 V
23
24
1 VCC 2
VCC
VCC 5 k
VCC 10 k
Filter pin for middle point of supply voltage. Pin voltage: approx. 6.0 V
VCC 20 k 22 F + 24 20 k 10 k
5 k
13
PC1853
Table 1-1 Explanation of Pins (7/8)
Pin Number 25 Pin Name OFC
VCC 10 k
Equivalent Circuit
Description Capacitor connection pin which absorbs offset voltage generated by phase shifter. Pin voltage: approx. 6.0 V
10 k VCC
25 +
22 F
26
Lin
VCC 60 k
L-channel signal input pin. Input impedance: 60 k Pin voltage: approx. 6.0 V
26
22 F
+
L-channel signal input
27
Rin
VCC 60 k
R-channel signal input pin. Input impedance: 60 k Pin voltage: approx. 6.0 V
27
22 F
+
R-channel signal input
28
LF1
1 k 18 k VCC
Low-pass filter. Pin voltage: approx. 6.0 V
28
680 pF
14
PC1853
Table 1-1 Explanation of Pins (8/8)
Pin Number 29 Pin Name MFO
1 k VCC 18 k
Equivalent Circuit
Description High-pass filter output pin for surround function (Simulated mode) (see 4.3 Surround Function). Pin voltage: approx. 6.0 V
29
30
MFI
820 k
0.082 F VCC
15 k 30 47 k
High-pass filter input pin for surround function (Simulated mode) (see 4.3 Surround Function). Pin voltage: approx. 6.0 V
15
PC1853
2. ATTENTIONS
<1> Attention on Pop Noise Reduction When changing the surround mode and switching power, use the mute function (approx. 200 ms) for pop noise reduction (see 4.4.1(2) Mute for the PC1853-01 or 4.4.2(1) Mute for the PC1853-02). <2> Attention on Supply Voltage Drive data on the I2C bus after supply voltage of total application system becomes stable.
16
PC1853
3. I2C BUS INTERFACE
The PC1853 has serial bus function. This serial bus (I2C bus) is a double wired bus developed by Philips. It is composed of 2 wires: serial clock line (SCL) and serial data line (SDA). The PC1853 has built-in I2C bus interface circuit, 9 rewritable registers (8 bits). SCL (Serial Clock Line) The master CPU outputs serial clock to synchronize with the data. According to this clock, the PC1853 takes in the serial data. Input level is compatible with CMOS. Clock frequency is 0 to 100 kHz. SDA (Serial Data Line) The master CPU outputs the data which is synchronized with serial clock. The PC1853 takes in this data according to the clock. Input level is compatible with CMOS. Fig. 3-1 Internal Equivalent Circuits of Interface Pin
RP SCL SDA
RP
PC1853
3.1 Data Transfer 3.1.1 Start condition Start condition is made by falling of SDA from "High" to "Low" during SCL is "High" as shown in Fig. 3-2. When this start condition is received, the PC1853 takes in the data synchronizing with the clock after that.
17
PC1853
3.1.2 Stop condition Stop condition is made by rising of SDA from "Low" to "High" during SCL is "High" as shown in Fig. 3-2. When this stop condition is received, the PC1853 stops to take in or output the data. Fig. 3-2 Start/Stop Condition of Data Transfer
3.5 V SDA 1.5 V 4.0 s MIN. 3.5 V SCL START 1.5 V STOP 4.7 s MIN.
3.1.3 Data transfer In the case of data transfer, data changing should be executed while SCL is "Low" like Fig. 3-3. When SCL is "High", be sure not to change the data. Fig. 3-3 Data Transfer
SDA
Note 1
Note 2
SCL
Note 1. Data hold time for I2C device: 300 ns MIN., Data hold time for CPU: 5 s MIN. 2. Data set-up time: 250 ns MIN. Remark Clock frequency: 0 to 100 kHz 3.2 Data Transfer Format Fig. 3-4 is an example of data transfer in write mode.
18
PC1853
Fig. 3-4 Example of Data Transfer in Write Mode
Slave address D6 D5 D4 D3 D2 D1 D0 W SDA
ACK
Subaddress D7 D6 D5 D4 D3 D2 D1 D0
ACK
Data D7 D6 D5 D4 D3 D2 D1 D0
ACK
SCL
Remark W: Write mode, ACK: Acknowledge bit Data is composed of 8 bits. Acknowledge bit is always added after this 8 bits data. Data should be transferred from MSB first. The 1 byte immediately after start condition specifies the slave address (chip address). This slave address is composed of 7 bits. Table 3-1 is the slave address of the PC1853. This slave address is registered by Phillips. Table 3-1 Slave Address of PC1853
Slave address Bias Voltage of ADS (Pin 22) 5V GND D6 1 1 D5 0 0 D4 0 0 D3 0 0 D2 1 1 D1 1 0 D0 0 0
User can set bit D1 freely. 0: Bias voltage of ADS (pin 22) is GND. 1: Bias voltage of ADS (pin 22) is 5 V. The remaining 1 bit is the read/write bit which specifies the direction of the data transferred after that. Set "0" because the PC1853 has write mode only. The byte following the slave address is subaddress byte of the PC1853. The PC1853 has 9 subaddresses from SA0 to SA8, and each of them is composed of 8 bits. The data to be set to the subaddress follows this subaddress byte. The PC1853 has automatic increment function. This function increments subaddress automatically in write mode. By using automatic increment function, once slave address and subaddress are set, data can be transferred continuously to the next subaddress. Use this function for initializing and so on. In the case of changing the data continuously of one subaddress (adjustment and so on), set the automatic increment function OFF (see 4.4.1(8) Automatic increment function). 3.2.1 1 byte data transfer The following is the format in the case of transferring 1 byte data.
S T A
SLAVE ADDRESS
A WC K
SUB ADDRESS
A C K
DATA
A C K
S T P
Remark STA: Start, W: Write mode, ACK: Acknowledge bit, STP: Stop
19
PC1853
3.2.2 Serial data transfer The following is the format in the case of transferring 8 bytes data at one time by using automatic increment function (the data of subaddress 01H to 08H, bit D6 is "1").
S T A
SLAVE ADDRESS
A WC K
SUB ADDRESS
A C K
DATA1
A C K
DATA2
A C K
DATA9
A C K
S T P
Remark STA: Start, W: Write mode, ACK: Acknowledge, STP: Stop The master CPU transfers "00H" as subaddress SA0 after start and slave address like above figure. It transfers the data of SA0 after subaddress, and then transfers the data of SA1, SA2..., SA8 continuously without transferring stop condition. Finally, it transfers stop condition and terminates. The increments of the subaddress of the PC1853 stops automatically when the subaddress comes to "08H" inside of it. 3.2.3 Acknowledge On I2C bus, acknowledge bit is added to the 9th bit after the data in order to judge whether data transfer has been succeeded or not. The master CPU judges it from "High" and "Low" of acknowledge condition. When this acknowledge period is "Low", it means success. And when the condition is "High", it means failure of transfer or forced release of bus as NAK state. The condition of being NAK state is when wrong slave address is transferred to slave IC or data transfer from slave side is finished in read state.
20
4.1 Subaddress List
4. EXPLANATION OF EACH COMMAND
(1) PC1853-01
Bit Subaddress 00H
MSB D7 Rear output selection 0: (L-R) 1: L-R 0
D6 Low boost 0: OFF 1: ON Automatic increment 0: OFF 1: ON
D5 Low boost gain 0: 6 dB 1: 3 dB
D4 Rear output mute 0: OFF 1: ON
D3 L+R signal output mute 0: OFF 1: ON
D2 Audio output mute 0: OFF 1: ON
D1 Main output mute 0: OFF 1: ON
LSB D0 Audio output control link 0: OFF 1: ON
01H
Attenuation volume Data
Main output volume control : Flat to Low : 111111 to 000000
02H
0
Automatic increment 0: OFF 1: ON
Balance control L-channel attenuation volume : R-channel attenuation volume : Data : Low Flat to to Flat Flat to to Flat Low
111111 to 100000 to 000000
03H
0
Automatic increment 0: OFF 1: ON Automatic increment 0: OFF 1: ON Automatic increment 0: OFF 1: ON Automatic increment 0: OFF 1: ON Automatic increment 0: OFF 1: ON
Gain Data Gain Data
Bass control : Boost to 0 dB to Cut : 111111 to 100000 to 000000 Treble control : Boost to 0 dB to Cut : 111111 to 100000 to 000000
04H
0
05H
0
L+R signal output volume control Attenuation volume : Flat to Low Data : 111111 to 000000 Attenuation volume Data Attenuation volume Data Units of phase shifters 0: 4 units 1: 1 unit Monaural/Stereo selection 0: Stereo 1: Monaural Effect : Data : Audio output volume control : Flat to Low : 111111 to 000000 Rear output volume control : Flat to Low : 111111 to 000000
06H
0
07H
0
PC1853
08H
Surround ON/OFF 0: OFF 1: ON
Automatic increment 0: OFF 1: ON
Effect control Large to Normal to Small 1111 to 1000 to 0000
21
Caution Be sure to write data "0" in the subaddress 01H to 07H, bit D7.
22
(2) PC1853-02
Bit Subaddress 00H
MSB D7 Rear output selection 0: (L-R) 1: L-R 0
D6 0
D5 0
D4 Rear output mute 0: OFF 1: ON
D3 L+R signal output mute 0: OFF 1: ON
D2 Audio output mute 0: OFF 1: ON
D1 0
LSB D0 0
01H
Automatic increment 0: OFF 1: ON
R-channel signal output (R1 OUT pin) volume control Attenuation volume : Flat to Low Data : 111111 to 000000
02H
0
Automatic increment 0: OFF 1: ON Automatic increment 0: OFF 1: ON Automatic increment 0: OFF 1: ON Automatic increment 0: OFF 1: ON Automatic increment 0: OFF 1: ON Automatic increment 0: OFF 1: ON Automatic increment 0: OFF 1: ON Units of phase shifters 0: 4 units 1: 1 unit
L-channel signal output (L1 OUT pin) volume control Attenuation volume : Flat to Low Data : 111111 to 000000 Gain Data Gain Data Bass control : Boost to 0 dB to Cut : 111111 to 100000 to 000000 Treble control : Boost to 0 dB to Cut : 111111 to 100000 to 000000
03H
0
04H
0
05H
0
L+R signal output volume control Attenuation volume : Flat to Low Data : 111111 to 000000 Attenuation volume Data Attenuation volume Data Monaural/Stereo selection 0: Stereo 1: Monaural Effect : Data : Audio output volume control : Flat to Low : 111111 to 000000 Rear output volume control : Flat to Low : 111111 to 000000 Effect control Large to Normal to Small 1111 to 1000 to 0000
06H
0
07H
0
08H
Surround ON/OFF 0: OFF 1: ON
PC1853
Caution Be sure to fix data of the subaddress 00H, bit D6, D5, D1, D0 and subaddress 01H to 07H, bit D7 to "0".
PC1853
4.2 Initialization After power-on, be sure to initialize the subaddress data to table below. Table 4-1 Initial Data of PC1853-01
Bit Subaddress 00H 01H 02H 03H 04H 05H 06H 07H 08H MSB D7 1 0 0 0 0 0 0 0 0 LSB D0 0 1 0 0 0 1 1 1 0
D6 0 1 1 1 1 1 1 1 1
D5 0 1 1 1 1 1 1 1 0
D4 0 1 0 0 0 1 1 1 0
D3 0 1 0 0 0 1 1 1 1
D2 0 1 0 0 0 1 1 1 0
D1 0 1 0 0 0 1 1 1 0
Table 4-2 Initial Data of PC1853-02
Bit Subaddress 00H 01H 02H 03H 04H 05H 06H 07H 08H MSB D7 1 0 0 0 0 0 0 0 0 LSB D0 0 1 1 0 0 1 1 1 0
D6 0 1 1 1 1 1 1 1 1
D5 0 1 1 1 1 1 1 1 0
D4 0 1 1 0 0 1 1 1 0
D3 0 1 1 0 0 1 1 1 1
D2 0 1 1 0 0 1 1 1 0
D1 0 1 1 0 0 1 1 1 0
Caution Until initializing completely, mute by the external units.
23
PC1853
4.3 Surround Function About the setting of surround mode, see table below. Table 4-3 Setting of Surround Mode
Setting Surround mode OFF Movie Music Simulated Subaddress: 08H D7 0 1 1 1 D5 - 0 1 0 D4 - 0 0 1 ON Surround ON/OFF OFF Description Units of phase shifter - 4 units 1 unit 4 units Monaural Monaural/Stereo selection - Stereo
-: Don't care. Caution When changing the surround mode, use the mute function (approx. 200 ms) for pop noise reduction (see 4.4.1(2) Mute for the PC1853-01 or 4.4.2(1) Mute for the PC1853-02).
24
PC1853
4.4 Explanation of Each Command 4.4.1 PC1853-01 (1) Audio Output Control Link By the data of subaddress 00H, bit D0, audio output volume link can be controlled (linked with main output control or not). Fig. 4-1 Audio Output Control Link
Subaddress D7 Rear output selection D6 Low boost D5 Low boost gain D4 Rear output mute D3 L+R signal output mute D2 Audio output mute D1 Main output mute D0 Audio output control link Audio output control link
00H
Audio output control link
0 Audio output volume controlled independently. Main output volume control (Subaddress: 01H, Bit: D5 to D0) Audio output volume control (Subaddress: 06H, Bit: D5 to D0) 1 Audio output volume control can be linked with main output volume control. Main output volume and audio output volume control (Subaddress: 01H, Bit: D5 to D0)
(2) Mute By the data of subaddress 00H, bit D1 to D4, ON/OFF of mute function can be controlled.
25
PC1853
Fig. 4-2 Mute (PC1853-01)
Subaddress D7 Rear output selection D6 Low boost D5 Low boost gain D4 Rear output mute D3 L+R signal output mute D2 Audio output mute D1 Main output mute D0 Audio output control link Main output mute 0 1 Main output not muted Main output muted
00H
Audio output mute 0 1 Audio output not muted Audio output muted
L+R signal output mute 0 1 L+R output not muted L+R output muted
Rear output mute 0 1 Rear output not muted Rear output muted
Caution Use the mute function (approx. 200 ms) for pop noise reduction when changing the surround mode and switching power. (3) Low boost function By the data of subaddress 00H, bit D5, the low boost gain can be selected (3 dB or 6 dB). And, by the data of subaddress 00H, bit D6 ON/OFF of the low boost can be controlled. Fig. 4-3 Low Boost Function
Subaddress D7 Rear output selection D6 Low boost D5 Low boost gain D4 Rear output mute D3 L+R signal output mute D2 Audio output mute D1 Main output mute D0 Audio output control link
00H
Low boost gain 0 1 Low boost gain: 6 dB Low boost gain: 3 dB
Low boost ON/OFF 0 1 Low boost: OFF Low boost: ON
26
PC1853
(4) Rear output selection By the data of subaddress 00H, bit D7, output signal of the rear output pin can be selected ( (L-R) signal or (L-R) signal). Fig. 4-4 Rear Output Selection (PC1853-01)
Subaddress D7 Rear output selection D6 Low boost D5 Low boost gain D4 Rear output mute D3 L+R signal output mute D2 Audio output mute D1 Main output mute D0 Audio output control link
00H
Rear output selection 0 1
(L-R) signal: Phase-shifted
(L-R) signal: Not phase-shifted
(5) Volume control By the data of subaddress 01H, 05H, 06H and 07H, bit D5 to D0, the volume control can be adjusted in 64 levels. Fig. 4-5 Volume Control (PC1853-01) (1/2) * Main output volume control
Subaddress D7 01H 0 D6 Automatic increment D5 D4 D3 D2 D1 D0
Main output volume control
Main output volume control Data D5 *** D0 111111 000000 Attenuation volume Flat Low
* L+R signal output volume control
Subaddress D7 05H 0 D6 Automatic increment D5 D4 D3 D2 D1 D0
L+R signal output volume control
L+R signal output volume control Data D5 *** D0 111111 000000 Attenuation volume Flat Low
27
PC1853
Fig. 4-5 Volume Control (PC1853-01) (2/2) * Audio output volume controlNote
Subaddress D7 06H 0 D6 Automatic increment D5 D4 D3 D2 D1 D0
Audio output volume control
Audio output volume control Data D5 *** D0 111111 000000 Attenuation volume Flat Low
Note When selecting the mode linking main output volume control to audio output volume control, the audio output volume can be controlled by the data of main output volume control (see (1) Audio Output Control Link). In that case, fix the audio output volume control data to "111111". * Rear output volume control
Subaddress D7 07H 0 D6 Automatic increment D5 D4 D3 D2 D1 D0
Rear output volume control
Rear output volume control Data D5 *** D0 111111 000000 Attenuation volume Flat Low
(6) Balance control By the data of subaddress 02H, bit D5 to D0, the balance level of L1 OUT and R1 OUT pin can be adjusted in 64 levels. Fig. 4-6 Balance Control
Subaddress D7 02H 0 D6 Automatic increment D5 D4 D3 D2 D1 D0
Balance control
Balance control L-channel Data attenuation D5 *** D0 volume 111111 100000 000000 Low Flat Flat
R-channel attenuation volume Flat Flat Low
28
PC1853
(7) Bass and treble control By the data of subaddress 03H and 04H, bit D5 to D0, the bass and treble tone for main output (L1 OUT and R1 OUT pin) can be adjusted in 64 levels. Fig. 4-7 Bass and Treble Control * Bass control
Subaddress D7 03H 0 D6 Automatic increment D5 D4 D3 D2 D1 D0
Bass control
Bass control Data D5 *** D0 111111 100000 000000 Gain Boost 0 dB Cut
* Treble control
Subaddress D7 04H 0 D6 Automatic increment D5 D4 D3 D2 D1 D0
Treble control
Treble control Data D5 *** D0 111111 100000 000000 Gain Boost 0 dB Cut
(8) Automatic increment function By the data of subaddress 01H to 08H, bit D6, ON/OFF of the automatic increment function can be controlled. Fig. 4-8 Automatic Increment Function
Subaddress D7 01H to 08H 0 D6 Automatic increment D5 D4 D3 D2 D1 D0
Main output volume control Automatic increment function 0 1 Automatic increment function: OFF Automatic increment function: ON
29
PC1853
Caution After power-on, be sure to initialize the subaddress data (see 4.2 Initialization). The automatic increment function increments subaddress automatically. Automatic increment function is ON : Subaddress is incremented automatically. If once slave address and subaddress are set, without setting the next subaddress, data of the next subaddress can be transferred. Automatic increment function is OFF: Subaddress is fixed. Data of the fixed subaddress can be set repeatedly. The automatic increment ON/OFF bit is in the subaddress 01H to 08H. The increment of subaddress is controlled individually by each automatic increment ON/OFF bit. As for 00H, subaddress is not incremented automatically (see 4.1 Subaddress List). For example, when the automatic increment function of subaddress 01H is ON and that of 02H is OFF, subaddress is incremented from 01H to 02H automatically and is fixed on 02H. In case of the automatic increment function of 08H is ON, subaddress is not incremented. If next data is transferred after setting data of 08H (acknowledge bit: L), the acknowledge condition is changed into NAK state (acknowledge bit: H). And the data transfer from the master CPU is stopped. (9) Effect control By the data of subaddress 08H, bit D3 to D0, the level of indirect sound signal (surround signal) added to the original signal can be adjusted in 16 levels. Fig. 4-9 Effect Control
Subaddress D7 08H Surround ON/OFF D6 Automatic increment D5 Units of phase shifters D4 Monaural/ stereo selection D3 D2 D1 D0
Effect control
Effect control Data D3 *** D0 1111 1000 0000 Effect Large Normal Small
(10) Monaural/Stereo selection By the data of subaddress 08H, bit D4, the surround mode can be selected (stereo mode or simulated mode). Stereo mode : Surround signal processing for stereo source. The phase of the difference between L-channel and R-channel signals is shifted and added to the original signal. Simulated mode : Stereo sound simulation for monaural source. The phase of the difference between the signal through HPF and the signal through LPF is shifted, and the signals are added to the original signal. When the output frequency characteristics of L-channel and R-channel signals become the form of comb, stereo sound simulation can be realized.
30
PC1853
Fig. 4-10 Monaural/Stereo Selection
Subaddress D7 08H Surround ON/OFF D6 Automatic increment D5 Units of phase shifters D4 Monaural/ stereo selection D3 D2 D1 D0
Effect control
Monaural/stereo selection 0 1 Stereo mode Simulated mode
(11) Units of phase shifters By the data of subaddress 08H, bit D5, the number of phase shifter's units (1 or 4 units) can be selected for the indirect sound signal (surround signal). Fig. 4-11 Units of Phase Shifters
Subaddress D7 08H Surround ON/OFF D6 Automatic increment D5 Units of phase shifters D4 Monaural/ stereo selection D3 D2 D1 D0
Effect control
Units of phase shifers 0 1 Phase shifter: 4 units Phase shifter: 1 unit
(12) Surround ON/OFF By the data of subaddress 08H, bit D7, ON/OFF of surround (indirect sound signal) mode can be selected. Surround OFF: Surround ON : Original signal is taken out directly (OFF mode). The signal passed through the phase shifter (indirect sound) is added to the original signal (Movie, Music and Simulated mode). Fig. 4-12 Surround ON/OFF
Subaddress D7 08H Surround ON/OFF D6 Automatic increment D5 Units of phase shifters D4 Monaural/ stereo selection D3 D2 D1 D0
Effect control
Surround ON/OFF 0 1 Surround: OFF Surround: ON
31
PC1853
4.4.2 PC1853-02 (1) Mute By the data of subaddress 00H, bit D2 to D4, ON/OFF of mute function can be controlled. Fig. 4-13 Mute (PC1853-02)
Subaddress D7 Rear output selection D6 D5 D4 Rear output mute D3 L+R signal output mute D2 Audio output mute D1 D0
00H
0
0
0
0
Audio output mute 0 1 Audio output not muted Audio output muted
L+R signal output mute 0 1 L+R output not muted L+R output muted
Rear output mute 0 1 Rear output not muted Rear output muted
Caution Use the mute function (approx. 200 ms) for pop noise reduction when changing the surround mode and switching power. (2) Rear output selection By the data of subaddress 00H, bit D7, output signal of the rear output pin can be selected ( (L-R) signal or (L-R) signal). Fig. 4-14 Rear Output Selection (PC1853-02)
Subaddress D7 Rear output selection D6 D5 D4 Rear output mute D3 L+R signal output mute D2 Audio output mute D1 D0
00H
0
0
0
0
Rear output selection 0 1
(L-R) signal: Phase-shifted
(L-R) signal: Not phase-shifted
32
PC1853
(3) Volume control By the data of subaddress 01H, 02H, 05H, 06H and 07H, bit D5 to D0, the volume control can be adjusted in 64 levels. Fig. 4-15 Volume Control (PC1853-02) (1/2) * R-channel output volume control
Subaddress D7 01H 0 D6 Automatic increment D5 D4 D3 D2 D1 D0
R-channel output volume control
R-channel output volume control Data D5 *** D0 111111 000000 R-channel attenuation volume Flat Low
* L-channel output volume control
Subaddress D7 02H 0 D6 Automatic increment D5 D4 D3 D2 D1 D0
L-channel output volume control
L-channel output volume control Data D5 *** D0 111111 000000 L-channel attenuation volume Flat Low
* L+R signal output volume control
Subaddress D7 05H 0 D6 Automatic increment D5 D4 D3 D2 D1 D0
L+R signal output volume control
L+R signal output volume control Data D5 *** D0 111111 000000 Attenuation volume Flat Low
33
PC1853
Fig. 4-15 Volume Control (PC1853-02) (2/2) * Audio output volume control
Subaddress D7 06H 0 D6 Automatic increment D5 D4 D3 D2 D1 D0
Audio output volume control
Audio output volume control Data D5 *** D0 111111 000000 Attenuation volume Flat Low
* Rear output volume control
Subaddress D7 07H 0 D6 Automatic increment D5 D4 D3 D2 D1 D0
Rear output volume control
Rear output volume control Data D5 *** D0 111111 000000 Attenuation volume Flat Low
(4) Bass and treble control See 4.4.1 (7) Bass and treble control. (5) Automatic increment function See 4.4.1 (8) Automatic increment function. (6) Effect control See 4.4.1 (9) Effect control. (7) Monaural/Stereo selection See 4.4.1 (10) Monaural/Stereo selection. (8) Units of phase shifters See 4.4.1 (11) Units of phase shifters. (9) Surround ON/OFF See 4.4.1 (12) Surround ON/OFF.
34
PC1853
5. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (Unless otherwise specified, TA = 25 C)
Parameter Supply voltage Input signal voltage I2C bus input pin voltage Power dissipation Operating temperature Storage temperature Symbol VCC VIN Vcont PD TA Tstg TA = 75 C VCC = 12 V No signal Test conditions Ratings 14.0 VCC VCC + 0.2 500 -20 to +75 -40 to +125 Unit V V V mW C C
Recommended Operating Conditions (Unless otherwise specified, TA = 25 C)
Parameter Supply voltage Input signal voltage I2C bus input pin voltage (H) I2C bus input pin voltage (L) Symbol VCC VIN VCC = 12 V, Gain of input-output: 0 dB Pins SDA and SCL Test conditions MIN. 10.8 0.0 TYP. 12.0 1.4 MAX. 13.2 7.9 Unit V Vp-p
VcontH VcontL
3.5 0.0
5.0 0.0
6.0 1.5
V V
35
36
Electrical Characteristics (VCC = 12 V, TA = 25 C, RH 70 %, f = 1 kHz, VIN = 0.5 Vrms, No load impedance, unless otherwise specified) General (1/1)
Switch modeNote Parameter Supply current Maximum input voltage 1 Symbol ICC VOM1 Test conditions S1 No signal Lin, Rin 2.8 Vrms, THD = 1 %, L1 OUT, R1 OUT, L2 OUT, R2 OUT, L+R OUT Maximum input voltage 2 VOM2 Lin 2.8 Vrms, Rin = GND, THD = 1 %, Rear OUT Distortion rate (L-ch) THDL f = 1 kHz, Lin = 0.5 Vrms, Rin = GND, L1 OUT, L2 OUT Distortion rate (R-ch) THDR f = 1 kHz, Lin = GND, Rin = 0.5 Vrms, R1 OUT, R2 OUT b a - - 0.1 0.5 % a b - 80 7F 60 60 60 7F 7F 7F 48 - 0.1 0.5 % a b - 2.5 2.8 3.3 Vp-p b a S2 b a S3 - - 00 01 02 03 04 05 06 07 08 80 7F 60 60 60 7F 7F 7F 48 80 7F 60 60 60 7F 7F 7F 48 16 7.9 24 8.8 32 9.3 mA Vp-p Subaddress data MIN. TYP. MAX. Unit
-: Don't care.
PC1853
Note See 7. MEASURING CIRCUIT. Remark The values are common to both the PC1853CT-01 and PC1853CT-02.
(1) PC1853CT-01 Volume control, tone control block (1/3)
Switch modeNote Parameter Volume attenuation 1 (1) Volume attenuation 1 (2) Volume attenuation 1 (3) Volume attenuation 2 (1) Volume attenuation 2 (2) Volume attenuation 2 (3) L+R volume attenuation 1 L+R volume attenuation 2 L+R volume attenuation 3 Rear volume attenuation 1 Rear volume attenuation 2 Balance attenuation (L-ch) 1 (1) Balance attenuation (L-ch) 1 (2) Balance attenuation (L-ch) 1 (3) Balance attenuation (R-ch) 1 (1) Balance attenuation (R-ch) 1 (2) Balance attenuation (R-ch) 1 (3) Low-band boost control Low-band flat control Low-band cut control Low-band boost control (6 dB) 1 Low-band boost control (6 dB) 2 Low-band boost control (6 dB) 3 Symbol ATTVL11 ATTVL12 ATTVL13 ATTVL21 ATTVL22 ATTVL23 ATTVLR1 ATTVLR2 ATTVLR3 ATTVRE1 ATTVRE2 ATTBL11 ATTBL12 ATTBL13 ATTBR11 ATTBR12 ATTBR13 VBB VBF VBC VB6dB1 VB6dB2 VB6dB3 f = 100 Hz, Lin = 0.5 Vrms, Rin = GND, L1 OUT a b - f = 100 Hz, Lin = 0.5 Vrms, Rin = GND, L1 OUT a b - Lin = GND, Rin = 0.5 Vrms, R1 OUT b a - Lin = 0.5 Vrms, Rin = GND, Rear OUT Lin = 0.5 Vrms, Rin = GND, L1 OUT a b - a b - Lin = 0.5 Vrms, Rin = 0.5 Vrms, L+R OUT a a - Lin = 0.5 Vrms, Rin = GND, L2 OUT a b - Test conditions Lin = 0.5 Vrms, Rin = GND, L1 OUT S1 a S2 b S3 - Subaddress data 00 01 02 03 04 05 06 07 08 80 7F 60 60 60 7F 7F 7F 48 60 40 80 7F 60 60 60 7F 7F 7F 48 60 40 80 7F 60 60 60 7F 7F 7F 48 60 40 80 7F 60 60 60 7F 7F 7F 48 60 80 7F 41 60 60 7F 7F 7F 48 60 7F 80 7F 41 60 60 7F 7F 7F 48 60 7F 80 7F 60 7F 60 7F 7F 7F 48 60 41 80 7F 60 60 60 7F 7F 7F 48 60 C0 50 MIN. -1.5 -25.0 -80.0 -1.5 -25.0 -80.0 -1.5 -25.0 -80.0 8.5 -15.0 -1.5 -1.5 -80.0 -80.0 -1.5 -1.5 7.0 -3.0 -13.0 2.0 3.0 4.0 TYP. 0.0 -19.0 - 0.0 -19.0 - 0.0 -19.0 - 10.0 -9.0 0.0 0.0 - - 0.0 0.0 10.0 0.0 -10.0 3.0 4.0 6.0 MAX. +1.5 -13.0 - +1.5 -13.0 - +1.5 -13.0 - 11.5 -3.0 +1.5 +1.5 - - +1.5 +1.5 13.0 +3.0 -7.0 4.0 5.0 8.0 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
PC1853
-: Don't care.
37
Note See 7. MEASURING CIRCUIT.
38
(1) PC1853CT-01 Volume control, tone control block (2/3)
Switch modeNote Parameter Low-band boost control (3 dB) 1 Low-band boost control (3 dB) 2 Low-band boost control (3 dB) 3 High-band boost control High-band flat control High-band cut control L, R in-phase gain difference 1 (1) L, R in-phase gain difference 1 (2) L, R in-phase gain difference 2 (1) L, R in-phase gain difference 2 (2) L, R in-phase gain difference 3 (1) L, R in-phase gain difference 3 (2) L, R in-phase gain difference 3 (3) L, R in-phase gain difference 4 (1) L, R in-phase gain difference 4 (2) L, R in-phase gain difference 4 (3) L, R in-phase gain difference 5 (1) L, R in-phase gain difference 5 (2) L, R in-phase gain difference 5 (3) L, R in-phase gain difference 6 (1) L, R in-phase gain difference 6 (2) L, R in-phase gain difference 6 (3) Symbol VB3dB1 VB3dB2 VB3dB3 VTB VTF VTC DG11 DG12 DG21 DG22 DG31 DG32 DG33 DG41 DG42 DG43 DG51 DG52 DG53 DG61 DG62 DG63 Lin = GND, Rin = 0.5 Vrms, L1 OUT, R1 OUT Lin = GND, Rin = 0.5 Vrms, L2 OUT, R2 OUT f = 100 Hz, Lin = 0.5 Vrms, Rin = 0.5 Vrms, L1 OUT, R1 OUT f = 10 kHz, Lin = 0.5 Vrms, Rin = 0.5 Vrms, L1 OUT, R1 OUT f = 100 Hz, Lin = 0.5 Vrms, Rin = 0.5 Vrms, L1 OUT, R1 OUT f = 100 Hz, Lin = 0.5 Vrms, Rin = 0.5 Vrms, L1 OUT, R1 OUT a a - a a - a a - a a - b a - b a - f = 10 kHz, Lin = 0.5 Vrms, Rin = GND, L1 OUT a b - Test conditions f = 100 Hz, Lin = 0.5 Vrms, Rin = GND, L1 OUT S1 a S2 b S3 - Subaddress data 00 01 02 03 04 05 06 07 08 A0 7F 60 60 60 7F 7F 7F 48 60 E0 50 80 7F 60 60 7F 7F 7F 7F 48 60 41 80 7F 60 60 60 7F 7F 7F 48 60 80 7F 60 60 60 7F 7F 7F 48 60 80 7F 60 7F 60 7F 7F 7F 48 60 41 80 7F 60 60 7F 7F 7F 7F 48 60 41 80 7F 60 60 60 7F 7F 7F 48 60 C0 48 A0 7F 60 60 60 7F 7F 7F 48 60 E0 48 MIN. 0.5 1.0 2.0 7.0 -3.0 -13.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 TYP. 1.5 2.0 3.0 10.0 0.0 -10.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 MAX. 2.5 3.0 4.0 13.0 +3.0 -7.0 +1.0 +1.0 +1.0 +1.0 +1.0 +1.0 +1.0 +1.0 +1.0 +1.0 +1.0 +1.0 +1.0 +1.0 +1.0 +1.0 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
-: Don't care.
PC1853
Note See 7. MEASURING CIRCUIT.
(1) PC1853CT-01 Volume control, tone control block (3/3)
Switch modeNote Parameter Muting attenuation 1 Symbol Mute 1 Test conditions Lin = 0.5 Vrms, Rin = GND, L1 OUT Muting attenuation 2 Mute 2 Lin = GND, Rin = 0.5 Vrms, R1 OUT Muting attenuation 3 Mute 3 Lin = 0.5 Vrms, Rin = GND, L2 OUT Muting attenuation 4 Mute 4 Lin = GND, Rin = 0.5 Vrms, R2 OUT Muting attenuation 5 Mute 5 Lin = 0.5 Vrms, Rin = 0.5 Vrms, L+R OUT Muting attenuation 6 Mute 6 (Rear) DC offset at muting mode (L1 OUT, R1 OUT) DC offset at muting mode (L2 OUT, R2 OUT) DC offset at muting mode (L+R OUT) DC offset at muting mode (Rear OUT) VOS4 VOS3 VOS2 VOS1 Lin = 0.5 Vrms, Rin = GND, Rear OUT No signal b b - 80 7F 60 60 60 7F 7F 7F 48 82 80 84 80 88 80 90 -50 0 +50 mV a b - 90 -70.0 - - dB a a - 88 -80.0 - - dB b a - -80.0 - - dB a b - 84 -80.0 - - dB b a - -80.0 - - dB S1 a S2 b S3 - Subaddress data 00 01 02 03 04 05 06 07 08 82 7F 60 60 60 7F 7F 7F 48 MIN. -80.0 TYP. - MAX. - Unit dB
-50
0
+50
mV
-50
0
+50
mV
-50
0
+50
mV
-: Don't care.
PC1853
Note See 7. MEASURING CIRCUIT.
39
40
(2) PC1853CT-02 Volume control, tone control block (1/2)
Switch modeNote Parameter Volume attenuation 1 (1) L-ch Volume attenuation 1 (2) L-ch Volume attenuation 1 (3) L-ch Volume attenuation 1 (4) R-ch Volume attenuation 1 (5) R-ch Volume attenuation 1 (6) R-ch Volume attenuation 2 (1) Volume attenuation 2 (2) Volume attenuation 2 (3) L+R volume attenuation 1 L+R volume attenuation 2 L+R volume attenuation 3 Rear volume attenuation 1 Rear volume attenuation 2 Low-band boost control Low-band flat control Low-band cut control High-band boost control High-band flat control High-band cut control L, R in-phase gain difference 1 (1) L, R in-phase gain difference 1 (2) L, R in-phase gain difference 2 (1) L, R in-phase gain difference 2 (2) Symbol ATTVL11 ATTVL12 ATTVL13 ATTVR14 ATTVR15 ATTVR16 ATTVL21 ATTVL22 ATTVL23 ATTVLR1 ATTVLR2 ATTVLR3 ATTVRE1 ATTVRE2 VBB VBF VBC VTB VTF VTC DG11 DG12 DG21 DG22 Lin = GND, Rin = 0.5 Vrms, L1 OUT, R1 OUT Lin = GND, Rin = 0.5 Vrms, L2 OUT, R2 OUT b a - b a - f = 100 kHz, Lin = 0.5 Vrms, Rin = GND, L1 OUT a b - Lin = 0.5 Vrms, Rin = GND, Rear OUT f = 100 Hz, Lin = 0.5 Vrms, Rin = GND, L1 OUT a b - a b - Lin = 0.5 Vrms, Rin = 0.5 Vrms, L+R OUT a a - Lin = 0.5 Vrms, Rin = GND, L2 OUT a b - Test conditions Lin = 0.5 Vrms, Rin = GND, L1 OUT Lin = GND, Rin = 0.5 Vrms, R1 OUT a b - S1 a S2 b S3 - Subaddress data 00 01 02 03 04 05 06 07 08 80 7F 7F 60 60 7F 7F 7F 48 60 40 80 7F 7F 60 60 7F 7F 7F 48 60 40 80 7F 7F 60 60 7F 7F 7F 48 60 40 80 7F 7F 60 60 7F 7F 7F 48 60 40 80 7F 7F 60 60 7F 7F 7F 48 60 80 7F 7F 7F 60 7F 7F 7F 48 60 41 80 7F 7F 60 7F 7F 7F 7F 48 60 41 80 7F 7F 60 60 7F 7F 7F 48 60 60 80 7F 7F 60 60 7F 7F 7F 48 60 MIN. -1.5 -25.0 -80.0 -1.5 -25.0 -80.0 -1.5 -25.0 -80.0 -1.5 -25.0 -80.0 8.5 -15.0 7.0 -3.0 -13.0 7.0 -3.0 -13.0 -1.0 -1.5 -1.0 -1.0 TYP. 0.0 -19.0 - 0.0 -19.0 - 0.0 -19.0 - 0.0 -19.5 - 10.0 -9.0 10.0 0.0 -10.0 10.0 0.0 -10.0 0.0 0.0 0.0 0.0 MAX. +1.5 -13.0 - +1.5 -13.0 - +1.5 -13.0 - +1.5 -13.0 - 11.5 -3.0 13.0 +3.0 -7.0 13.0 +3.0 -7.0 +1.0 +1.5 +1.0 +1.0 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
PC1853
dB
-: Don't care. Note See 7. MEASURING CIRCUIT.
(2) PC1853CT-02 Volume control, tone control block (2/2)
Switch modeNote Parameter L, R in-phase gain difference 3 (1) L, R in-phase gain difference 3 (2) L, R in-phase gain difference 3 (3) L, R in-phase gain difference 4 (1) L, R in-phase gain difference 4 (2) L, R in-phase gain difference 4 (3) Muting attenuation 1 Symbol DG31 DG32 DG33 DG41 DG42 DG43 Mute 1 Test conditions f = 100 Hz, Lin = 0.5 Vrms, Rin = 0.5 Vrms, L1 OUT, R1 OUT f = 10 kHz, Lin = 0.5 Vrms, Rin = 0.5 Vrms, L1 OUT, R1 OUT Lin = 0.5 Vrms, Rin = GND, L2 OUT Muting attenuation 2 Mute 2 Lin = GND, Rin = 0.5 Vrms, R2 OUT Muting attenuation 3 Mute 3 Lin = 0.5 Vrms, Rin = 0.5 Vrms, L+R OUT Muting attenuation 4 Mute 4 (Rear) DC offset at muting mode (L1 OUT, R1 OUT) DC offset at muting mode (L2 OUT, R2 OUT) DC offset at muting mode (L+R OUT) DC offset at muting mode (Rear OUT) VOS4 VOS3 VOS2 VOS1 Lin = 0.5 Vrms, Rin = GND, Rear OUT No signal b b - 80 7F 7F 60 60 7F 7F 7F 48 82 80 84 80 88 80 90 -50 0 +50 mV a b - 90 -70.0 - - dB a a - 88 -80.0 - - dB b a - -80.0 - - dB a b - a a - S1 a S2 a S3 - Subaddress data 00 01 02 03 04 05 06 07 08 80 7F 7F 7F 60 7F 7F 7F 48 60 41 80 7F 7F 60 7F 7F 7F 7F 48 60 41 84 7F 7F 60 60 7F 7F 7F 48 MIN. -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -80.0 TYP. 0.0 0.0 0.0 0.0 0.0 0.0 - MAX. +1.0 +1.0 +1.0 +1.0 +1.0 +1.0 - Unit dB dB dB dB dB dB dB
-50
0
+50
mV
-50
0
+50
mV
-50
0
+50
mV
PC1853
-: Don't care. Note See 7. MEASURING CIRCUIT.
41
42
Matrix surround block (1/2)
Switch modeNote1 Parameter In-phase gain Movie mode 1 Note2 In-phase gain Movie mode 2 Note2 In-phase gain Music mode 1 In-phase gain Music mode 2 In-phase gain Simulated mode (L-ch) 1 In-phase gain Simulated mode (L-ch) 2 In-phase gain Simulated mode (L-ch) 3 In-phase gain Simulated mode (R-ch) 1 In-phase gain Simulated mode (R-ch) 2 Note2 In-phase gain Simulated mode (R-ch) 3 Note2 GSIMR3
Note2 Note2 Note2 Note2 Note2 Note2
Subaddress data 00 01 02 03 04 05 06 07 08 80 7F 60 60 60 7F 7F 7F C8 MIN. 3.0 TYP. 7.0 MAX. 11.0 Unit dB
Symbol GMOV1
Test conditions f = 1 kHz, Lin = 0.5 Vrms, Rin = GND, L1 OUT
S1 a
S2 b
S3 -
GMOV2
f = 1 kHz, Lin = 0.5 Vrms, Rin = GND, R1 OUT
0.0
4.0
8.0
dB
GMUS1
f = 1 kHz, Lin = 0.5 Vrms, Rin = GND, L1 OUT
E8
3.5
5.5
7.5
dB
GMUS2
f = 1 kHz, Lin = 0.5 Vrms, Rin = GND, R1 OUT
-2.5
-0.5
+1.5
dB
GSIML1
f = 250 Hz, Lin = 0.5 Vrms, Rin = 0.5 Vrms, L1 OUT
a
a
-
D8
-0.5
+3.5
+6.5
dB
GSIML2
f = 1 kHz, Lin = 0.5 Vrms, Rin = 0.5 Vrms, L1 OUT
-
-3.0
+4.5
dB
GSIML3
f = 4 kHz, Lin = 0.5 Vrms, Rin = 0.5 Vrms, L1 OUT
2.0
6.0
10.0
dB
GSIMR1
f = 250 Hz, Lin = 0.5 Vrms, Rin = 0.5 Vrms, R1 OUT
D8
-
-5.5
-1.0
dB
GSIMR2
f = 1 kHz, Lin = 0.5 Vrms, Rin = 0.5 Vrms, R1 OUT f = 4 kHz, Lin = 0.5 Vrms, Rin = 0.5 Vrms, R1 OUT
0.0
3.0
6.0
dB
-
-7.0
+5.0
dB
-: Don't care. Note 1. See 7. MEASURING CIRCUIT. 2. See 4.3 Surround Function about setting of surround mode. Remark The values are common to both the PC1853CT-01 and PC1853CT-02.
PC1853
Matrix surround block (2/2)
Switch modeNote Parameter Output noise Symbol NO1 Test conditions Lin = GND, Rin = GND, Surround: OFF, DIN-AUDIO filter, L1 OUT, R1 OUT, L2 OUT, R2 OUT, L+R OUT, Rear OUT Crosstalk 1 CT1 Lin = 0.5 Vrms, Rin = GND, 0 dB: 0.5 Vrms Crosstalk 2 CT2 Lin = GND, Rin = 0.5 Vrms, 0 dB: 0.5 Vrms Inter-mode offset VOSM No signal. At surround mode switching. b b - 80 7F 60 60 60 7F 7F 7F xF -50 0 +50 mV b a - - -80 -70 dB a b - 80 7F 60 60 60 7F 7F 7F 48 - -80 -70 dB S1 b S2 b S3 - Subaddress data 00 01 02 03 04 05 06 07 08 80 7F 60 60 60 7F 7F 7F 48 MIN. - TYP. 25 MAX. 50 Unit
Vrms
-: Don't care. Note See 7. MEASURING CIRCUIT. Remark The values are common to both the PC1853CT-01 and PC1853CT-02.
PC1853
43
44
ELECTRICAL CHARACTERISTICS MEASUREMENT LIST Set subaddress data as shown in 4.2 Initialization unless otherwise specified. General (1/1)
Data Parameter Supply current Symbol ICC Current flowing to pin 15. No signal Maximum input voltage 1 VOM1 Input signal level of pins 13, 14, 16 and 17. Distortion rate of pins 13, 14, 16 and 17: 1 % Pins 26 and 27: Input SIN wave (1 kHz, 2.8 Vrms). Maximum input voltage 2 VOM2 Input signal level of pin 11. Distortion rate of pin 11: 1 % Pin 26: Input SIN wave (1 kHz, 2.8 Vrms). Pin 27: No signal Distortion rate (L-ch) THDL Distortion rate of pins 14 and 17. Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor). Distortion rate (R-ch) THDR Distortion rate of pins 13 and 16. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz, 0.5 Vrms). Test conditions Subaddress D7 D6 D5 D4 D3 D2 D1 D0
Remark The methods are common to both the PC1853CT-01 and PC1853CT-02.
PC1853
(1) PC1853CT-01 Volume control, tone control block (1/9)
Data Parameter Volume attenuation 1 (1) Symbol ATTVL11 Volume attenuation = 20 log Volume attenuation 1 (2) ATTVL12 Test conditions L1 output L input 0 1 1 0 0 0 0 0 Subaddress 01 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 1 1 1 1
L1 output: Output signal level of pin 14. L input: Input signal level of pin 26.
Volume attenuation 1 (3)
ATTVL13
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor).
0
1
0
0
0
0
0
0
Volume attenuation 2 (1)
ATTVL21 Volume attenuation = 20 log
L2 output L input
06
0
1
1
1
1
1
1
1
Volume attenuation 2 (2)
ATTVL22
L2 output: Output signal level of pin 17. L input: Input signal level of pin 26.
0
1
1
0
0
0
0
0
Volume attenuation 2 (3)
ATTVL23
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor).
0
1
0
0
0
0
0
0
L+R volume attenuation 1
ATTVLR1 L+R volume attenuation = 20 log
L+R output L, R input
05
0
1
1
1
1
1
1
1
L+R volume attenuation 2
ATTVLR2
L+R output: Output signal level of pin 12. L, R input: Input signal level of pin 26 or 27.
0
1
1
0
0
0
0
0
L+R volume attenuation 3
ATTVLR3
Pin 26, 27: Input SIN wave (1 kHz, 0.5 Vrms).
0
1
0
0
0
0
0
0
Rear volume attenuation 1
ATTVRE1 Rear volume attenuation = 20 log
Rear output L input
07
0
1
1
1
1
1
1
1
Rear output: Output signal level of pin 11. Rear volume attenuation 2 ATTVRE2 L input: Input signal level of pin 26. Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor). 0 1 1 0 0 0 0 0
PC1853
45
46
(1) PC1853CT-01 Volume control, tone control block (2/9)
Data Parameter Balance attenuation (L-ch) 1 (1) Symbol ATTBL11 Balance attenuation = 20 log Balance attenuation (L-ch) 1 (2) ATTBL12 Test conditions L1 output L input 0 1 1 0 0 0 0 0 Subaddress 02 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 1
L1 output: Output signal level of pin 14. L input: Input signal level of pin 26.
Balance attenuation (L-ch) 1 (3)
ATTBL13
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor).
0
1
1
1
1
1
1
1
Balance attenuation (R-ch) 1 (1)
ATTBR11 Balance attenuation = 20 log
R1 output R input
02
0
1
0
0
0
0
0
1
Balance attenuation (R-ch) 1 (2)
ATTBR12
R1 output: Output signal level of pin 13. R input: Input signal level of pin 27.
0
1
1
0
0
0
0
0
Balance attenuation (R-ch) 1 (3)
ATTBR13
Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
0
1
1
1
1
1
1
1
Low-band boost control
VBB Bass response = 20 log
L1 output L input
03
0
1
1
1
1
1
1
1
Low-band flat control
VBF
L1 output: Output signal level of pin 14. L input: Input signal level of pin 26.
0
1
1
0
0
0
0
0
Low-band cut control
VBC
Pin 26: Input SIN wave (100 Hz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor).
0
1
0
0
0
0
0
1
Low-band boost control (6 dB) 1
VB6dB1 Bass response = 20 log
VBON VBOFF
00
1
0 1 1 0 1 1
0
0
0
0
0
0
VBON: Output signal level of pin 14 (Low boost: ON). Low-band boost control (6 dB) 2 VB6dB2 VBOFF: Output signal level of pin 14 (Low boost: OFF). Pin 26: Input SIN wave (100 Hz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor).
01 00
0 1
1 0
1 0
1 0
1 0
1 0
1 0
01
0
1
0
0
0
0
0
PC1853
(1) PC1853CT-01 Volume control, tone control block (3/9)
Data Parameter Low-band boost control (6 dB) 3 Symbol VB6dB3 Bass response = 20 log VBON VBOFF Test conditions Subaddress 00 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 0 0 0 0 0
VBON : Output signal level of pin 14 (Low boost: ON). VBOFF: Output signal level of pin 14 (Low boost: OFF). Pin 26: Input SIN wave (100 Hz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor). Low-band boost control (3 dB) 1 VB3dB1 Bass response = 20 log VBON VBOFF 01 00 0 1 01 00 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0
VBON : Output signal level of pin 14 (Low boost: ON). Low-band boost control (3 dB) 2 VB3dB2 VBOFF: Output signal level of pin 14 (Low boost: OFF). Pin 26: Input SIN wave (100 Hz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor). Low-band boost control (3 dB) 3 VB3dB3
1 1
1 0
1 0
1 0
1 0
1 0
01 00
0 1
1 1
0 0
0 0
0 0
0 0
0 0
01 High-band boost control VTB Treble response = 20 log High-band flat control VTF L1 output L input 04
0 0
0 1
1 1
0 1
0 1
0 1
0 1
L1 output: Output signal level of pin 14. L input: Input signal level of pin 26.
0
1
1
0
0
0
0
0
High-band cut control
VTC
Pin 26: Input SIN wave (10 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor).
0
1
0
0
0
0
0
1
PC1853
47
48
(1) PC1853CT-01 Volume control, tone control block (4/9)
Data Parameter L, R in-phase gain difference 1 (1) Symbol DG11 Channel to channel error = 20 log Test conditions R1 output R input - ATTVL11 Subaddress 01 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 1 1 1 1
R1 output: Output signal level of pin 13. R input: Input signal level of pin 27. ATTVL11: Gain of the Volume attenuation 1 (1). Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz, 0.5 Vrms). L, R in-phase gain difference 1 (2) DG12 Channel to channel error = 20 log R1 output R input - ATTVL12 0 1 1 0 0 0 0 0
R1 output: Output signal level of pin 13. R input: Input signal level of pin 27. ATTVL12: Gain of the Volume attenuation 1 (2). Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz, 0.5 Vrms). L, R in-phase gain difference 2 (1) DG21 Channel to channel error = 20 log R2 output R input - ATTVL21 06 0 1 1 1 1 1 1 1
R2 output: Output signal level of pin 16. R input: Input signal level of pin 27. ATTVL21: Gain of the Volume attenuation 2 (1). Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz, 0.5 Vrms). L, R in-phase gain difference 2 (2) DG22 Channel to channel error = 20 log R2 output R input - ATTVL22 0 1 1 0 0 0 0 0
R2 output: Output signal level of pin 16. R input: Input signal level of pin 27.
PC1853
ATTVL22: Gain of the Volume attenuation 2 (2). Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
(1) PC1853CT-01 Volume control, tone control block (5/9)
Data Parameter L, R in-phase gain difference 3 (1) Symbol DG31 Channel to channel error = 20 log Test conditions R1 output R input - VBB Subaddress 03 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 1 1 1 1
R1 output: Output signal level of pin 13. R input: Input signal level of pin 27. VBB: Gain of the Low-band boost control. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (100 Hz, 0.5 Vrms). L, R in-phase gain difference 3 (2) DG32 Channel to channel error = 20 log R1 output R input - VBF 0 1 1 0 0 0 0 0
R1 output: Output signal level of pin 13. R input: Input signal level of pin 27. VBF: Gain of the Low-band flat control. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (100 Hz, 0.5 Vrms). L, R in-phase gain difference 3 (3) DG33 Channel to channel error = 20 log R1 output R input - VBC 0 1 0 0 0 0 0 1
R1 output: Output signal level of pin 13. R input: Input signal level of pin 27. VBC: Gain of the Low-band cut control. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (100 Hz, 0.5 Vrms). L, R in-phase gain difference 4 (1) DG41 Channel to channel error = 20 log R1 output R input - VTB 05 0 1 1 1 1 1 1 1
PC1853
R1 output: Output signal level of pin 13. R input: Input signal level of pin 27. VTB: Gain of the High-band boost control.
49
Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (10 kHz, 0.5 Vrms).
50
(1) PC1853CT-01 Volume control, tone control block (6/9)
Data Parameter L, R in-phase gain difference 4 (2) Symbol DG42 Channel to channel error = 20 log Test conditions R1 output R input - VTF Subaddress 05 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 0 0 0 0
R1 output: Output signal level of pin 13. R input: Input signal level of pin 27. VTF: Gain of the High-band flat control. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (10 kHz, 0.5 Vrms). L, R in-phase gain difference 4 (3) DG43 Channel to channel error = 20 log R1 output R input - VTC 0 1 0 0 0 0 0 1
R1 output: Output signal level of pin 13. R input: Input signal level of pin 27. VTC: Gain of the High-band cut control. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (10 kHz, 0.5 Vrms). L, R in-phase gain difference 5 (1) DG51 Channel to channel error = 20 log VBON VBOFF - VB6dB1 00 1 0 1 0 0 0 0 0 0
VBON : Output signal level of pin 13 (Low boost: ON). VBOFF : Output signal level of pin 13 (Low boost: OFF). VB6dB1: Gain of the Low-band boost control (6 dB) 1. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (100 Hz, 0.5 Vrms). L, R in-phase gain difference 5 (2) DG52 Channel to channel error = 20 log VBON VBOFF - VB6dB2 00 1 01 0
1
1
1
1
1
1
1
0 1
0
0
0
0
0
0
VBON : Output signal level of pin 13 (Low boost: ON). VBOFF : Output signal level of pin 13 (Low boost: OFF).
PC1853
VB6dB2: Gain of the Low-band boost control (6 dB) 2. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (100 Hz, 0.5 Vrms). 01 0 1 1 0 0 0 0 0
(1) PC1853CT-01 Volume control, tone control block (7/9)
Data Parameter L, R in-phase gain difference 5 (3) Symbol DG53 Channel to channel error = 20 log Test conditions VBON VBOFF - VB6dB3 Subaddress 00 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 0 0 0 0 0
VBON : Output signal level of pin 13 (Low boost: ON). VBOFF : Output signal level of pin 13 (Low boost: OFF). VB6dB3: Gain of the Low-band boost control (6 dB) 3. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (100 Hz, 0.5 Vrms). L, R in-phase gain difference 6 (1) DG61 Channel to channel error = 20 log VBON VBOFF - VB3dB1 00 1 01 0
1
0
0
1
0
0
0
0 1
1
0
0
0
0
0
VBON : Output signal level of pin 13 (Low boost: ON). VBOFF: Output signal level of pin 13 (Low boost: OFF). VB3dB1: Gain of the Low-band boost control (3 dB) 1. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (100 Hz, 0.5 Vrms). L, R in-phase gain difference 6 (2) DG62 Channel to channel error = 20 log VBON VBOFF - VB3dB2 00 1 01 0
1
1
1
1
1
1
1
0 1
1
0
0
0
0
0
VBON : Output signal level of pin 13 (Low boost: ON). VBOFF: Output signal level of pin 13 (Low boost: OFF). VB3dB2: Gain of the Low-band boost control (3 dB) 2. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (100 Hz, 0.5 Vrms). L, R in-phase gain difference 6 (3) DG63 Channel to channel error = 20 log VBON VBOFF - VB3dB3 00 1 01 0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
PC1853
VBON : Output signal level of pin 13 (Low boost: ON). VBOFF : Output signal level of pin 13 (Low boost: OFF). VB3dB3: Gain of the Low-band boost control (3 dB) 3.
1
51
Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (100 Hz, 0.5 Vrms).
01
0
1
0
0
1
0
0
0
52
(1) PC1853CT-01 Volume control, tone control block (8/9)
Data Parameter Muting attenuation 1 Symbol Mute 1 Mute 1 = 20 log L1 output L input Test conditions Subaddress 00 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 1 0
L1 output : Output signal level of pin 14. L input: Input signal level of pin 26. Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor). Muting attenuation 2 Mute 2 Mute 2 = 20 log R1 output R input
R1 output : Output signal level of pin 13. R input: Input signal level of pin 27. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz, 0.5 Vrms). Muting attenuation 3 Mute 3 Mute 3 = 20 log L2 output L input 1 0 0 0 0 1 0 0
L2 output : Output signal level of pin 17. L input: Input signal level of pin 26. Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor). Muting attenuation 4 Mute 4 Mute 4 = 20 log R2 output R input
R2 output : Output signal level of pin 16. R input: Input signal level of pin 27. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
PC1853
(1) PC1853CT-01 Volume control, tone control block (9/9)
Data Parameter Muting attenuation 5 Symbol Mute 5 Mute 5 = 20 log L+R output L, R input Test conditions Subaddress 00 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 0 0 0
L+R output : Output signal level of pin 12. L, R input: Input signal level of pin 26 or 27. Pins 26 and 27: Input SIN wave (1 kHz, 0.5 Vrms). Muting attenuation 6 Mute 6 (Rear) Mute 6 = 20 log Rear output L input 1 0 0 1 0 0 0 0
Rear output : Output signal level of pin 11. L input: Input signal level of pin 26. Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor). DC offset at muting mode (L1 OUT, R1 OUT) VOS1 VOS1 = V1 - V0 V1: DC voltage of pin 14 or 13 (Main output mute: ON). V0: DC voltage of pin 14 or 13 (Main output mute: OFF). Pins 26 and 27: Connect to GND with an input coupling capacitor. DC offset at muting mode (L2 OUT, R2 OUT) VOS2 VOS2 = V1 - V0 V1: DC voltage of pin 17 or 16 (Audio output mute: ON). V0: DC voltage of pin 17 or 16 (Audio output mute: OFF). Pins 26 and 27: Connect to GND with an input coupling capacitor. DC offset at muting mode (L+R OUT) VOS3 VOS3 = V1 - V0 V1: DC voltage of pin 12 (L+R output mute: ON). V0: DC voltage of pin 12 (L+R output mute: OFF). Pins 26 and 27: Connect to GND with an input coupling capacitor. 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 00 1 0 0 0 0 0 0 1 0
PC1853
DC offset at muting mode (Rear OUT)
VOS4
VOS4 = V1 - V0 V1: DC voltage of pin 11 (Rear output mute: ON). V0: DC voltage of pin 11 (Rear output mute: OFF).
1
0
0
0 1
0
0
0
0
53
Pins 26 and 27: Connect to GND with an input coupling capacitor.
54
(2) PC1853CT-02 Volume control, tone control block (1/6)
Data Parameter Volume attenuation 1 (1) L-ch Symbol ATTVL11 Volume attenuation = 20 log Volume attenuation 1 (2) L-ch ATTVL12 Test conditions L1 output L input 0 1 1 0 0 0 0 0 Subaddress 02 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 1 1 1 1
L1 output: Output signal level of pin 14. L input: Input signal level of pin 26.
Volume attenuation 1 (3) L-ch
ATTVL13
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor).
0
1
0
0
0
0
0
0
Volume attenuation 1 (4) R-ch
ATTVR14 Volume attenuation = 20 log
R1 output R input
01
0
1
1
1
1
1
1
1
Volume attenuation 1 (5) R-ch
ATTVR15
R1 output: Output signal level of pin 13. R input: Input signal level of pin 27.
0
1
1
0
0
0
0
0
Volume attenuation 1 (6) R-ch
ATTVR16
Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz, 0.5 Vrms).
0
1
0
0
0
0
0
0
Volume attenuation 2 (1)
ATTVL21 Volume attenuation = 20 log
L2 output L input
06
0
1
1
1
1
1
1
1
Volume attenuation 2 (2)
ATTVL22
L2 output: Output signal level of pin 17. L input: Input signal level of pin 26.
0
1
1
0
0
0
0
0
Volume attenuation 2 (3)
ATTVL23
Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor).
0
1
0
0
0
0
0
0
L+R volume attenuation 1
ATTVLR1 L+R volume attenuation = 20 log
L+R output L, R input
05
0
1
1
1
1
1
1
1
L+R volume attenuation 2
ATTVLR2
L+R output: Output signal level of pin 12. L, R input: Input signal level of pin 26 or 27.
0
1
1
0
0
0
0
0
L+R volume attenuation 3
ATTVLR3
Pin 26, 27: Input SIN wave (1 kHz, 0.5 Vrms).
0
1
0
0
0
0
0
0
PC1853
(2) PC1853CT-02 Volume control, tone control block (2/6)
Data Parameter Rear volume attenuation 1 Symbol ATTVRE1 Rear volume attenuation = 20 log Test conditions Rear output L input Subaddress 07 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 1 1 1 1
Rear output: Output signal level of pin 11. Rear volume attenuation 2 ATTVRE2 L input: Input signal level of pin 26. Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor). Low-band boost control VBB Bass response = 20 log Low-band flat control VBF L1 output L input 0 1 1 0 0 0 0 0 03 0 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0
L1 output: Output signal level of pin 14. L input: Input signal level of pin 26.
Low-band cut control
VBC
Pin 26: Input SIN wave (100 Hz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor).
0
1
0
0
0
0
0
1
High-band boost control
VTB Treble response = 20 log
L1 output L input
04
0
1
1
1
1
1
1
1
High-band flat control
VTF
L1 output: Output signal level of pin 14. L input: Input signal level of pin 26.
0
1
1
0
0
0
0
0
High-band cut control
VTC
Pin 26: Input SIN wave (10 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor).
0
1
0
0
0
0
0
1
L, R in-phase gain difference 1 (1)
DG11 Channel to channel error = 20 log
R1 output R input - ATTVL11
01 02
0
1
1
1
1
1
1
1
R1 output : Output signal level of pin 13. R input: Input signal level of pin 27. ATTVL11: Gain of the Volume attenuation 1 (1). Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz, 0.5 Vrms). Same method about L-ch input/output signal
PC1853
55
56
(2) PC1853CT-02 Volume control, tone control block (3/6)
Data Parameter L, R in-phase gain difference 1 (2) Symbol DG12 Channel to channel error = 20 log Test conditions R1 output R input - ATTVL12 Subaddress 01 02 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 0 0 0 0
R1 output : Output signal level of pin 13. R input: Input signal level of pin 27. ATTVL12: Gain of the Volume attenuation 1 (2). Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz, 0.5 Vrms). Same method about L-ch input/output signal L, R in-phase gain difference 2 (1) DG21 Channel to channel error = 20 log R2 output R input - ATTVL21 06 0 1 1 1 1 1 1 1
R2 output : Output signal level of pin 16. R input: Input signal level of pin 27. ATTVL21: Gain of the Volume attenuation 2 (1). Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz, 0.5 Vrms). L, R in-phase gain difference 2 (2) DG22 Channel to channel error = 20 log R2 output R input - ATTVL22 0 1 1 0 0 0 0 0
R2 output : Output signal level of pin 16. R input: Input signal level of pin 27. ATTVL22: Gain of the Volume attenuation 2 (2). Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz, 0.5 Vrms). L, R in-phase gain difference 3 (1) DG31 Channel to channel error = 20 log R1 output R input - VBB 03 0 1 1 1 1 1 1 1
R1 output : Output signal level of pin 13.
PC1853
R input: Input signal level of pin 27. VBB: Gain of the Low-band boost control. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (100 Hz, 0.5 Vrms).
(2) PC1853CT-02 Volume control, tone control block (4/6)
Data Parameter L, R in-phase gain difference 3 (2) Symbol DG32 Channel to channel error = 20 log Test conditions R1 output R input - VBF Subaddress 03 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 0 0 0 0
R1 output : Output signal level of pin 13. R input: Input signal level of pin 27. VBF: Gain of the Low-band flat control. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (100 Hz, 0.5 Vrms). L, R in-phase gain difference 3 (3) DG33 Channel to channel error = 20 log R1 output R input - VBC 0 1 0 0 0 0 0 1
R1 output : Output signal level of pin 13. R input: Input signal level of pin 27. VBC: Gain of the Low-band cut control. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (100 Hz, 0.5 Vrms). L, R in-phase gain difference 4 (1) DG41 Channel to channel error = 20 log R1 output R input - VTB 05 0 1 1 1 1 1 1 1
R1 output : Output signal level of pin 13. R input: Input signal level of pin 27. VTB: Gain of the High-band boost control. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (10 kHz, 0.5 Vrms). L, R in-phase gain difference 4 (2) DG42 Channel to channel error = 20 log R1 output R input - VTF 0 1 1 0 0 0 0 0
PC1853
R1 output : Output signal level of pin 13. R input: Input signal level of pin 27. VTF: Gain of the High-band flat control.
57
Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (10 kHz, 0.5 Vrms).
58
(2) PC1853CT-02 Volume control, tone control block (5/6)
Data Parameter L, R in-phase gain difference 4 (3) Symbol DG43 Channel to channel error = 20 log Test conditions R1 output R input - VTC Subaddress 05 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 1
R1 output : Output signal level of pin 13. R input: Input signal level of pin 27. VTC: Gain of the High-band cut control. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (10 kHz, 0.5 Vrms). Muting attenuation 1 Mute 1 Mute 1 = 20 log L2 output L input 00 1 0 0 0 0 1 0 0
L2 output : Output signal level of pin 17. L input: Input signal level of pin 26. Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor). Muting attenuation 2 Mute 2 Mute 2 = 20 log R2 output R input
R2 output : Output signal level of pin 16. R input: Input signal level of pin 27. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz, 0.5 Vrms). Muting attenuation 3 Mute 3 Mute 3 = 20 log L+R output L, R input 1 0 0 0 1 0 0 0
L+R output : Output signal level of pin 12. L, R input: Input signal level of pin 26 or 27. Pins 26 and 27: Input SIN wave (1 kHz, 0.5 Vrms).
PC1853
(2) PC1853CT-02 Volume control, tone control block (6/6)
Data Parameter Muting attenuation 4 Symbol Mute 4 (Rear) Mute 4 = 20 log Rear output L input Test conditions Subaddress 00 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 0 0
Rear output : Output signal level of pin 11. L input: Input signal level of pin 26. Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor). DC offset at muting mode (L1OUT, R1 OUT) VOS1 VOS1 = V1 - V0 V1: DC voltage of pin 14 or 13 (Main output mute: ON). V0: DC voltage of pin 14 or 13 (Main output mute: OFF). Pins 26 and 27: Connect to GND with an input coupling capacitor. DC offset at muting mode (L2 OUT, R2 OUT) VOS2 VOS2 = V1 - V0 V1: DC voltage of pin 17 or 16 (Audio output mute: ON). V0: DC voltage of pin 17 or 16 (Audio output mute: OFF). Pins 26 and 27: Connect to GND with an input coupling capacitor. DC offset at muting mode (L+R OUT) VOS3 VOS3 = V1 - V0 V1: DC voltage of pin 12 (L+R output mute: ON). V0: DC voltage of pin 12 (L+R output mute: OFF). Pins 26 and 27: Connect to GND with an input coupling capacitor. DC offset at muting mode (Rear OUT) VOS4 VOS4 = V1 - V0 V1: DC voltage of pin 11 (Rear output mute: ON). V0: DC voltage of pin 11 (Rear output mute: OFF). Pins 26 and 27: Connect to GND with an input coupling capacitor. 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 00 1 0 0 0 0 0 0 1 0
PC1853
59
60
Matrix surround block (1/3)
Data Parameter In-phase gain Movie mode 1 Symbol GMOV1 Response = 20 log Test conditions L1, R1 output L input Subaddress 08 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 1 0 0 0
L1, R1 output: Output signal level of pin 14 or 13. In-phase gain Movie mode 2 GMOV2 L input: Input signal level of pin 26. Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor). In-phase gain Music mode 1 GMUS1 Response = 20 log L1, R1 output L input 08 1 1 1 0 1 0 0 0
L1, R1 output: Output signal level of pin 14 or 13. In-phase gain Music mode 2 GMUS2 L input: Input signal level of pin 26. Pin 26: Input SIN wave (1 kHz, 0.5 Vrms). Pin 27: No signal (Connect to GND with an input coupling capacitor). In-phase gain Simulated mode (L-ch) 1 GSIML1 Response = 20 log L1 output L, R input 08 1 1 0 1 1 0 0 0
L1 output : Output signal level of pin 14. L, R input: Input signal level of pin 26 or 27. Pins 26 and 27: Input SIN wave (250 Hz, 0.5 Vrms).
In-phase gain Simulated mode (L-ch) 2
GSIML2 Response = 20 log
L1 output L, R input
L1 output : Output signal level of pin 14. L, R input: Input signal level of pin 26 or 27. Pins 26 and 27: Input SIN wave (1 kHz, 0.5 Vrms).
In-phase gain Simulated mode (L-ch) 3
GSIML3 Response = 20 log
L1 output L, R input
L1 output : Output signal level of pin 14.
PC1853
L, R input: Input signal level of pin 26 or 27. Pins 26 and 27: Input SIN wave (4 kHz, 0.5 Vrms).
Remark The methods are common to both the PC1853CT-01 and PC1853CT-02.
Matrix surround block (2/3)
Data Parameter In-phase gain Simulated mode (R-ch) 1 Symbol GSIMR1 Response = 20 log Test conditions R1 output L, R input Subaddress 08 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 1 0 0 0
R1 output: Output signal level of pin 13. L, R input: Input signal level of pin 26 or 27. Pins 26 and 27: Input SIN wave (250 Hz, 0.5 Vrms).
In-phase gain Simulated mode (R-ch) 2
GSIMR2 Response = 20 log
R1 output L, R input
R1 output: Output signal level of pin 13. L, R input: Input signal level of pin 26 or 27. Pins 26 and 27: Input SIN wave (1 kHz, 0.5 Vrms).
In-phase gain Simulated mode (R-ch) 3
GSIMR3 Response = 20 log
R1 output L, R input
R1 output : Output signal level of pin 13. L, R input: Input signal level of pin 26 or 27. Pins 26 and 27: Input SIN wave (4 kHz, 0.5 Vrms).
Output noise
NO1
NO1: Output noise voltage of pins 11, 12, 13, 14, 16 and 17. Pins 26 and 27: Connect to GND with an input coupling capacitor. Filter of noise meter: DIN-AUDIO filter
Crosstalk 1
CT1 Crosstalk = 20 log
R output L input
R output: Output signal level of pin 13 or 16. L input: Input signal level of pin 26. Pin 26: Input SIN wave (1 kHz. 0.5 Vrms).
PC1853
Pin 27: No signal (Connect to GND with an input coupling capacitor).
Remark The methods are common to both the PC1853CT-01 and PC1853CT-02.
61
62
Matrix surround block (3/3)
Data Parameter Crosstalk 2 Symbol CT2 Crosstalk = 20 log L output R input Test conditions Subaddress D7 D6 D5 D4 D3 D2 D1 D0
L output : Output signal level of pin 14 or 17. R input: Input signal level of pin 27. Pin 26: No signal (Connect to GND with an input coupling capacitor). Pin 27: Input SIN wave (1 kHz. 0.5 Vrms). Inter-mode offset VOSM No signal. At surround mode switching.Note 08 x 1 x x 1 1 1 1
Note See 4.3 Surround Function. Remark The methods are common to both the PC1853CT-01 and PC1853CT-02.
PC1853
PC1853
6. CHARACTERISTIC CURVES
About surround mode, see 4.3 Surround Function. 6.1 Frequency Response Characteristics in Each Mode (1) OFF mode (L-channel, R-channel)
VCC = 12 V VIN = 1.4 Vp-p (= 0 dB) 8
6
4
Gain G (dB)
2
0
-2
-4
-6
100
1k Frequency f (Hz)
10 k
63
PC1853
(2) Movie Mode
10 VCC = 12 V Lin: VIN = 1.4 Vp-p (= 0 dB) Rin: GND L1 OUT R1 OUT
5
0
-5
Gain G (dB)
-10
-15
-20
-25
-30
-35 100 1k Frequency f (Hz) 10 k
(3) Music Mode
12 VCC = 12 V Lin: VIN = 1.4 Vp-p (= 0 dB) Rin: GND L1 OUT R1 OUT
8
4
0
Gain G (dB)
-4
-8
-12
-16
-18
-20 100 1k Frequency f (Hz) 10 k
64
PC1853
(4) Simulated Mode
12 VCC = 12 V Lin, Rin: VIN = 1.4 Vp-p (= 0 dB) L1 OUT R1 OUT
8
4
0
Gain G (dB)
-4
-8
-12
-16
-20
100
1k Frequency f (Hz)
10 k
65
PC1853
6.2 Characteristics of Phase Shifter and Rear Output (1) Movie Mode
0
VCC = 12 V Lin: VIN = 1.4 Vp-p (=0 dB) Rin: GND Rear OUT pin Characteristics of +100 Phase Shifter Characteristics of Rear Output
-10
0
-20
-100
10
30
50 70 100
300 500700 1 k Frequency f (Hz)
3k
5 k 7 k 10 k
20 k
(2) Music Mode
VCC = 12 V Lin: VIN = 1.4 Vp-p (=0 dB) Rin: GND Rear OUT pin Characteristics of Phase Shifter +100 Characteristics of Rear Output
0
-10
0
-20
-100
10
30
50 70 100
300 500 700 1 k Frequency f (Hz)
3k
5 k 7 k 10 k
20 k
66
Phase (deg.)
Gain G (dB)
Phase (deg.)
Gain G (dB)
PC1853
(3) Simulated Mode
VCC = 12 V Lin, Rin: VIN = 1.4 Vp-p (=0 dB) Rear OUT pin Characteristics of Phase Shifter Characteristics of Rear Output
0
+100
-10
0
-20
-100
10
30
50 70 100
300 500 700 1 k Frequency f (Hz)
3k
5 k 7 k 10 k
20 k
Phase (deg.)
Gain G (dB)
67
PC1853
6.3 Control Characteristics (1) Volume Control Characteristics
0 OFF mode f = 1 kHz Lin or Rin: VIN = 1.4 Vp-p (=0 dB) Lin or Rin: GND
-20
-40
Attenuation (dB)
-60
-80
-100
000000
001000
010000
011000
100000
101000
110000
111000
111111
Data of Subaddress: 01H (D5******D0)
(2) Balance Control Characteristics
0 OFF mode f = 1 kHz L1 OUT Lin: VIN = 1.4 Vp-p (=0 dB) Rin: GND R1 OUT Lin: GND Rin: VIN = 1.4 Vp-p (=0 dB)
-20
-40 Attenuation (dB) Lch Rch -60 flat ATT Lch Rch ATT flat
-80
-100
000000
001000
010000
011000
100000
101000
110000
111000
111111
Data of Subaddress: 02H (D5******D0)
68
PC1853
(3) Tone Control Characteristics (Bass)
10 OFF mode Bass: f = 100 Hz Lin: VIN = 1.4 Vp-p (=0 dB) Rin: GND L1 OUT
5
Attenuation (dB)
0
-5
-10
000000
001000
010000
011000
100000
101000
110000
111000
111111
Data of Subaddress: 03H (D5******D0)
(4) Tone Control Characteristics (Treble)
10 OFF mode Treble: f = 10 kHz Lin: VIN = 1.4 Vp-p (=0 dB) Rin: GND L1 OUT
5
Attenuation (dB)
0
-5
-10
000000
001000
010000
011000
100000
101000
110000
111000
111111
Data of Subaddress: 04H (D5******D0)
69
PC1853
(5) Tone Frequency Characteristics
20
A
F
OFF mode Lin: VIN = 1.4 Vp-p (=0 dB) Rin: GND L1 OUT
Curve Subaddress Data (D5 *****D0) 111111 110000 03H 100000 010000 000001 111111 110000 04H 100000 010000 000001
10 B G
A B C
Gain G (dB)
C 0
H
D E F
D
I
G H
-10 E J
I J
-20 10 100 1k Frequency f (Hz) 10 k 100 k
(6) Low Boost Control Characteristics
10
5
OFF mode f = 100 Hz Lin: VIN = 1.4 Vp-p (= 0 dB) Rin : GND L1 OUT Low Boost 1 (6 dB) Low Boost 2 (3 dB)
Attenuation (dB)
0
-5
-10
000000
001000
010000
011000
100000
101000
110000
111000
111111
Data of Subaddress: 01H (D5*****D0)
70
PC1853
(7) Low Boost 1 (6 dB)
20
VCC = 12 V Lin: VIN = 1.4 Vp-p (= 0 dB) Rin: GND L1 OUT A
Curve
0
Subaddress
Data (D5 *****D0) 111111
A B
B
01H
100000 010000
C
Gain G (dB)
-20
C
-40
-60 10 100 1k Frequency f (Hz) 10 k 100 k
(8) Low Boost 2 (3 dB)
20
VCC = 12 V Lin: VIN = 1.4 Vp-p (= 0 dB) Rin: GND L1 OUT A
0
Curve A B
Subaddress
Data (D5 *****D0) 111111
01H
100000 010000
Gain G (dB)
B -20
C
C -40
-60 10 100 1k Frequency f (Hz) 10 k 100 k
71
PC1853
(9) Effect Control Characteristics
10 f = 1 kHz Lin: VIN = 1.4 Vp-p (= 0 dB) Rin: GND Rear OUT pin 0 dB : Subaddress: 08 H, Data "1000" Movie Mode Music Mode Simulated Mode
0
-10 Attenuation (dB)
-20
-30
-40
0000
0100
1000 Data of Subaddress: 08H (D3******D0)
1100
1111
72
PC1853
6.4 Input/Output Characteristics, Distortion Rate
f = 1 kHz Lin or Rin: VIN = 1.4 Vp-p (= 0 dB) Lin or Rin: GND PC1853-01 Subaddress: 01H, Data "111111" Subaddress: 02H, Data "100000" PC1853-02 Subaddress: 01H, 02H, Data "111111" Output Signal Voltage Distortion Rate
5.0
5.0
Output Signal Voltage (Vrms)
1.0 0.5
1.0 0.5
0.1 0.05
0.1 0.05
0.01 0.05 0.1 0.5 1.0 Input Signal Voltage (Vrms) 5.0
Distortion Rate (%)
73
PC1853
7. MEASURING CIRCUIT
L, R channel signal input DVDD (+5 V) DGND b a I2C bus DGND SDA SCL L channel signal 2 output R channel signal 2 output
Switch 3 ab ba Switch 1 Switch 2
820 k
Note
3.3 F 3.3 F + + + + + + 0.082 F BAL-C VOL-C 680 pF 22 F 22 F 22 F 22 F OFC 1/2 VCC DGND ADS SDA SCL (RVC) (LVC) L2 OUT R2 OUT MFI MFO LF1 Rin Lin 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Note Note
PC1853CT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FC1 FC2 FC3 FC4 LF2 RTC RBC LTC LBC Rear OUT L+R OUT R1 OUT L1 OUT VCC AGND Note Note Note Note Note Note Note Note Note 0.01 F 0.1 F 2200 pF 0.022 F 0.022 F1000 pF 6800 pF 0.1 F 6800 pF 0.1 F + 47 F
AGND
Rear L+R Routput signal channel output signal1 output
Lchannel signal1 output
AVCC (+12 V)
Note
Recommended external parts. Carbon-film resistor : Film capacitor Ceramic capacitor : : 1 % 1 % 1 %
Attention on Printed Wiring 1. AGND: Wide area grounding. 2. Connect terminating resistors as near pins 26 and 27 as possible. 3. Make the wiring of I2C bus block distant from the wiring of analog block. 4. Connect by-pass capacitor near pin 15 (VCC pin).
Use external parts as follows unless otherwise specified. Carbon-film resistor : Film capacitor : Electrolytic capacitor : 5 % 20 % 20 %
74
PC1853
8. PACKAGE DIMENSIONS
30PIN PLASTIC SHRINK DIP (400 mil)
30 16
1
A
15
K I L
J
H G
F D N
M
C B
M
R
NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 28.46 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.85 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 10.16 (T.P.) 8.6 0.25 +0.10 -0.05 0.17 0~15
INCHES 1.121 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.033 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.400 (T.P.) 0.339 0.010 +0.004 -0.003 0.007 0~15 S30C-70-400B-1
75
PC1853
[MEMO]
Caution: Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product.
M4 94.11

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